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|||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||||||||||||||||||||||||||||||||||||||||||||| real - time clock module (i 2 c bus ) 12 - 07 - 0001 pt 0321 - 6 07/04 /12 1 pt7c43 38 33 product features ? using external 32.768khz quartz crystal ? supports i 2 c - bus's high speed mode (400 khz) ? includes time (h our /m inute /s econd ) and calendar (y ear /m onth /d ate /d ay ) counter functions (bcd code) ? programmable square wave output signal ? 56 - byte, batt ery - backed, nonvolatile (nv) ram for data storage ? automatic power - fail detect and swit ch circuitry of battery backup ? ul recognized : e348121 product description the pt7c43 38 serial real - time clock is a low - power clock/calendar with a programmable square - wave output and 56 bytes of nonvolatile ram . address and data are transferred serially via a 2 - wire, bidirectional bus. the clock/calendar provides seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automa tically adjusted for months with fewer than 31 days, including corrections for leap year. the clock operates in either the 24 - hour or 12 - hour format with am/pm indicator. the pt7c43 38 series ha ve a built - in power sense circuit that detects power failures and automatically switches to the battery supply. table 1 shows the basic functions of pt7c43 38 . more details are shown in section: overview of functions. table 1. basic functions of pt7c43 38 item function pt7c43 38 1 oscillator source: crystal: 32.768khz ? oscillator enable/disable ? oscillator fail detect ? 2 time time display 12 - hour ? 24 - hour ? century bit - 3 alarm interrupt - 4 programmable square wave output (hz) 1, 4.096k, 8.192k, 32.768k 5 ram 56 ? 8 6 battery backup ?
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 2 pt7c43 38 33 real - time clock module (i 2 c bus) pin assignment pin description pin no. pin type description 1 x1 i 32.768khz cr ystal connections. the internal oscillator circuitry is designed for operation with a crystal having a specified load capacitance (cl) of 12.5pf. pin x1 is the input to the oscillator and can optionally be connected to an external 32.768khz oscillator. the output of the internal oscillator, pin x2, is floated if an external oscillator is connected to pin x1. an external 32.768khz oscillator can also drive the pt7c4338. in this configuration, the x1 pin is connected to the external oscillator signal and the x2 pin is floated. 2 x2 o 6 scl i serial clock input. scl is used to synchronize data movement on the i 2 c serial interface. 5 sda i/o serial data input/output. sda is the input/output pin for the 2 - wire serial interface. the sda pin is open - drain outpu t and requires an external pull - up resistor. 7 sqw/out o square - wave/output driver. when enabled and the sqwe bit set to 1, the sqw/out pin outputs one of four square - wave frequencies (1hz, 4khz, 8khz, 32khz). it is open drain and requires an external pu ll up resistor. operates with either vcc or vbat applied. 8 vcc p supply voltage. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. when a backup supply is connected to the device and vcc is bel ow vpf, reads and writes are inhibited. however, the timekeeping function continues unaffected by the lower input voltage. 3 vbat p +3v battery input. backup supply input for any standard 3v lithium cell or other energy source. battery voltage must be hel d between the minimum and maximum limits for proper operation. if a backup supply is not required, vbat must be grounded. ul recognized to ensure against reverse charging when used with a lithium battery. 4 gnd p ground. dc power is provided to the device on these pins. vcc is the primary power input. when voltage is applied within normal limits, the device is fully accessible and data can be written and read. when a backup supply is connected to the device and vcc is below vpf, reads and writes are inhibi ted. however, the timekeeping function continues unaffected by the lower input voltage. x2 vbat gnd vcc sqw/out scl 6 7 8 1 2 3 x1 4 5 sda pt7c4338 soic-8 msop-8
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 3 pt7c43 38 33 real - time clock module (i 2 c bus) function block maximum ratings storage temperature ................................ ................................ ................................ ............... - 55 o c to +125 o c ambient temperature with power applied ................................ ................................ ...... - 40 o c to +85 o c supply voltage to ground potential (vcc to gnd) ................................ ..................... - 0.3v to +6.5v dc input (all other inputs except vcc & gnd) ................................ ........................... - 0.3v to +6.5v dc output voltage (sda, /inta, /intb pins) ................................ .............................. - 0.3v to +6.5v dc output current (fout) ................................ ................................ ................................ .. - 0.3v to (v cc +0.3v ) power dissipatio n ................................ ................................ ................................ .................... 320mw (depend on package) no te: stresses greater than those listed under maximum ratings may cause permanent damage to the device. this is a stress rating on ly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (v cc = v cc(min) to v cc(max) , t a = - 40 to +85 .) (note 1) parameter symbol conditions min. typ . max. unit supply voltage v cc pt7c433833 2.7 3.3 5.5 v logic 1 v ih note 2 0.7 * v cc - v cc + 0.3 logic 0 v il note 2 - 0.3 - +0.3 * v cc power - fail voltage v pf pt7c433833 - 2.59 - v bat battery voltage v bat note 2 1.5 3.0 3.7 note 1: limits at - 40c are guaranteed by design and not production tested. note 2: all voltages are referenced to ground.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 4 pt7c43 38 33 real - time clock module (i 2 c bus) dc electrical characteristics (v cc = v cc(min) to v cc(max) , t a = - 40 to +85 .) (note 1) parameter symbol conditions min. typ. max. unit v bat battery voltage v bat note 2 1.5 - 3.7 v input leakage i li note 3 - - 1 a lo note 4 - - 1 a olsda v cc > 2v; v ol = 0.4v 3.0 - - ma v cc < 2v; v ol = 0.2 v cc 3.0 - - sqw/out logic 0 output i olsqw v cc > 2v; v ol = 0.4v 3.0 - - ma 1.71v < v cc < 2v; v ol = 0.2 v cc 3.0 - - 1.5v < v cc < 1.71v; v ol = 0.2 v cc 250 - - a cca pt7c433833 - 120 200 a ccs pt7c433833 - 85 125 a bat leakage current (v cc active) i batlkg - - 25 100 na (v cc = 0v, t a = - 40 to +85 .) (note 1) parameter symbol min. typ. max. unit v bat current (osc on); v bat =3.7v, sqw/out off (note 7) i batosc1 - 400 1200 na v bat current (osc on); v bat =3.7v, sqw/out on (32khz) (note 7) i batosc2 - 570 1400 na v bat data - retention current (osc off); v bat =3.7v (note 7) i batdat - - 300 na note 1: limits at - 40c are guaranteed by design and not production tested. note 2: all voltages are referenced to ground. note 3: scl only. note 4: sda and sqw/out. note 5: icca ------ scl clocking at max frequency = 400khz. note 6: specified with the i2c bus inactive. note 7: measured with a 32.768khz crystal attached to x1 and x2. ac electrical characteristics sym description value unit v hm rising and falling threshold voltage high 0. 7 v cc v v hl rising and falling threshold voltage low 0. 3 v cc v measurement level signal t f t r v hm v lm
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 5 pt7c43 38 33 real - time clock module (i 2 c bus) (t a = - 40 to +85 ) (note 1) parameter symbol condit ions min. typ. max. unit scl clock frequency f scl fast mode 100 - 400 khz standard mode - - 100 bus free time between stop and start condition t buf fast mode 1.3 - - s hd:sta fast mode 0.6 - - s low fast mode 1.3 - - s high fast mode 0.6 - - s su:sta fast mode 0.6 - - s hd:sta fast mode 0 - 0.9 s su:sta fast mode 100 - - ns standard mode 250 - - rise time of both sda and scl signals (note 6) t r f ast mode 20+0.1 c b - 300 ns standard mode 20+0.1c b - 1000 fall time of both sda and scl signals (note 6) t f fast mode 20+0.1c b - 300 ns standard mode 20+0.1c b - 300 setup time for stop condition t su:sto fast mode 0.6 - - s b note 6 - - 400 pf i/o capacitance (sda, scl) c i/o note 1 - - 10 pf oscillator stop flag (osf) delay t osf note 7 - 100 - ms note 1: limits of full temperature are guaranteed by design not production test. note 2: after this period, the first clock pulse is generated. note 3: a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ihmin of the scl signal) to bridge the undefined region of the falling edge of scl. note 4: the maximum t hd:dat need only be met if the device does not stretch the low period (t low ) of the scl signal. note 5: a fast - mode device can be used in a standard - mode system, but the requirement t su:dat to 250ns must then be met. this is automatically th e case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max + t su:dat = 1000 + 250 = 1250ns before the scl line is released. note 6: c b ------ total capacitance of one bus line in pf. note 7: the parameter t osf is the time period the oscillator must be stopped for the osf flag to be set over the voltage range of 0.0v vcc vcc max and 1.3v vbat 3.7v.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 6 pt7c43 38 33 real - time clock module (i 2 c bus) timing diagram power - up/power - down c haracteristics (t a = - 40 to +85 ) (note 1 , fig 3 ) para meter symbol min. typ. max. unit recovery at power - up (note 2) t rec - - 2 ms v cc fall time: v pf(max) to v pf(min) t vccf 300 - - s cc rise time: v pf(min) to v pf(max) t vccr 0 - - s note 1: limits at - 40c are guaranteed by design and not production tes ted. note 2: this delay applies only if the oscillator is enabled and running. if the oscillator is disabled or stopped, no power - up delay occurs. fig 3. power - up/power - down timing
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 7 pt7c43 38 33 real - time clock module (i 2 c bus) recommended layout for crystal built - in capacitors specificati ons and recommended external capacitors parameter symbol typ unit build - in capacitors x1 to gnd c g 20 pf x2 to gnd c d 20 pf recommended external capacitors x1 to gnd c 1 4 pf x2 to gnd c 2 4 pf note : the frequency of crystal can be optimized by exter nal capacitor c 1 and c 2 , for frequency=32.768khz, c 1 and c 2 should meet the equation as below: cpar + [(c 1 +c g )*(c 2 +c d )]/ [(c 1 +c g )+(c 2 +c d )] =c l cpar is all parasitical capacitor between x1 and x2. c l is crystals load capacitance. crystal specifications p arameter symbol min typ max unit nominal frequency f o - 32.768 - khz series resistance esr - - 70 k ? l - 12.5 - pf note : the crystal, traces and crystal input pins should be isolated from rf generating signals.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 8 pt7c43 38 33 real - time clock module (i 2 c bus) function description overview of functions clock function cpu can read or write data including the year (last two digits), month, date, day, hour, minute, and second. any (two - digit) year that is a multiple of 4 is treated as a leap year and calculated automatically as such until the year 2 100 . programmable square wave output a square wave output enable bit controls s quare wave output at pin 7. 4 frequencies are selectable: 1, 4.096k, 8.192k, 32.768k hz. interface with cpu data is read and written via the i 2 c bus interface using two signal lines: scl (clock) and sda (data). since the output of the i/o pin sda is open drain, a pull - up resistor should be used on the circuit board if the cpu output i/o is also open drain. the scl's maximum clock frequency is 400 khz, which supports the i 2 c bus's high - speed mode. oscillator enable/disable oscillator can be enabled or disab led by /eosc bit. registers allocation of registers addr. (hex) *1 function register definition bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 seconds (00 - 59) /eosc *2 s40 s20 s10 s8 s4 s2 s1 01 minutes (00 - 59) 0 m40 m20 m10 m8 m4 m2 m1 02 hours (00 - 23 / 01 - 12) 0 12, /24 h20 or p, /a h10 h8 h4 h2 h1 03 days of the week (01 - 07) 0 0 0 0 0 w4 w2 w1 04 dates (01 - 31) 0 0 d20 d10 d8 d4 d2 d1 05 months (01 - 12) 0 0 0 mo10 mo8 mo4 mo2 mo1 06 years (00 - 99) y80 y40 y20 y10 y8 y4 y2 y1 07 control *3 out *4 0 osf sqwe *5 0 0 rs1 *6 rs0 *6 08~3f ram *7 - - - - - - - - caution points: *1. pt7c43 38 uses 6 bits for address. that is if write data to 41h, the data will be written to 01h address register. *2. oscillator enable bit. when this bit is set to 1, os cillator is stopped but time count chain is still active. *3. control register was used to select sqw/out pin output square wave with one of 4 kinds of frequency or dc level. *4. control sqw/out pin output dc level when square wave is disabled. *5. s quare wave outputs enable at sqw/out pin. *6. square wave output frequency select. *7. pt7c43 38 has 56 ? 8 static ram for customer use. it is volatile ram. *8. all bits marked with " 0 " are read - only bits. their value when read is always "0". all bits m arked with " - " are customer using space.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 9 pt7c43 38 33 real - time clock module (i 2 c bus) control and status register addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 07 control out 0 osf sqwe 0 0 rs1 rs0 (default) 1 0 1 1 0 0 1 1 ? out it controls the output level of the sqw/out pin when the squar e wave output is disabled. out data description read / write 0 when sqwe = 0, sqw/out pin output low. 1 when sqwe = 0, sqw/out pin output high. default ? sqwe (square wave enable) this bit, when set to logic 1, will enable the osc illator output. the frequency of the square wave output depends upon the value of the rs0 and rs1 bits. with the square wave output set to 1hz, the clock registers update on the falling edge of the square wa ve. ? rs (rate select) these bits control the freq uency of the square wave output when the square wave output has been enabled. rs1, rs0 data sqw output freq. (hz) read / write 00 1 01 4.096k 10 8.192k 11 32.768k default ? osf (oscillator stop flag) logic 1 in this bit indicates that the oscillat or either is stopped or was stopped for some period of time and may be used to judge the validity of the clock and calendar data. this bit is set to logic 1 anytime that the oscillator stops. the following are examples of conditions that can cause the osf bit to be set: 1) the first time power is applied. 2) the voltage present on vcc and vbat is insufficient to support oscillation. 3) the /eosc bit is set to 1, disabling the oscillator . 4) external influences on the crystal (e.g., noise, leakage, etc.). this bit remains at logic 1 until written to logic 0. this bit can only be written to logic 0. attempting to write osf bit to logic 1 leaves the value unchanged.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 10 pt7c43 38 33 real - time clock module (i 2 c bus) time counter time digit display (in bcd code): ? second digits: range from 00 to 59 and carried to minute digits when incremented from 59 to 00. ? minute digits: range from 00 to 59 and carried to hour digits when incremented from 59 to 00. ? hour digits: see description on the /12, 24 bit. carried to day and day - of - the - week digits when incremented from 11 p.m. to 12 a.m. or 23 to 00. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 00 seconds /eosc s40 s20 s10 s8 s4 s2 s1 (default) 0 undefined undefined undefined undefined undefined undefined undefined 01 minutes 0 m40 m20 m10 m8 m4 m2 m1 (default) 0 u ndefined undefined undefined undefined undefined undefined undefined 02 hours 0 12, /24 h20 or p,/a h10 h8 h4 h2 h1 (default) 0 undefined undefined undefined undefined undefined undefined undefined ? 12, /24 bit this bit is used to select between 12 - hou r clock system and 24 - hour clock system. 12, /24 data description read / write 0 24 - hour system 1 12 - hour system this bit is used to select between 12 - hour clock operation and 24 - hour clock operation. 12, /24 description hours register 0 24 - hour ti me display 1 12 - hour time display * be sure to select between 12 - hour and 24 - hour clock operation before writing the time data. 24 - hour clock 12 - hour clock 24 - hour clock 12 - hour clock 00 52 ( am 12 ) 12 72 ( pm 12 ) 01 41 ( am 01 ) 13 61 ( pm 01 ) 02 42 ( am 02 ) 14 62 ( pm 02 ) 03 43 ( am 03 ) 15 63 ( pm 03 ) 04 44 ( am 04 ) 16 64 ( pm 04 ) 05 45 ( am 05 ) 17 65 ( pm 05 ) 06 46 ( am 06 ) 18 66 ( pm 06 ) 07 47 ( am 07 ) 19 67 ( pm 07 ) 08 48 ( am 08 ) 20 68 ( pm 08 ) 09 49 ( am 09 ) 21 69 ( pm 09 ) 10 50 ( am 10 ) 22 70 ( pm 10 ) 11 51 ( am 11 ) 23 71 ( pm 11 )
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 11 pt7c43 38 33 real - time clock module (i 2 c bus) days of the week counter the day counter is a divide - by - 7 counter that counts from 01 to 07 and up 07 before starting agai n from 01. values that correspond to the day of week are user defined but must be sequential (i.e., if 1 equals sunday, then 2 equals monday, and so on). illog ical time and date entries result in undefined operation. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 03 days of the week 0 0 0 0 0 w4 w2 w1 (default) 0 0 0 0 0 undefined undefined undefined calendar counter the data format is bcd format. ? day digits: range from 1 to 31 (for january, march, may, july, august, october and december). range fro m 1 to 30 (for april, june, september and november). range from 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary years). carried to month digits when cycled to 1. ? month digits: range from 1 to 12 and carried to year digits when cycled to 1. ? year digits: range from 00 to 99 and 00, 04, 08, , 92 and 96 are counted as leap years. addr. (hex) description d7 d6 d5 d4 d3 d2 d1 d0 04 dates 0 0 d20 d10 d8 d4 d2 d1 (default) 0 0 undefined undefined undefined undefined undefine d undefined 05 months 0 0 0 m10 m8 m4 m2 m1 (default) 0 0 0 undefined undefined undefined undefined undefined 06 years y80 y40 y20 y10 y8 y4 y2 y1 (default) undefined undefined undefined undefined undefined undefined undefined undefined note: any re gistered imaginary time should be replaced by correct time, otherwise it will cause the clock counter malfunction.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 12 pt7c43 38 33 real - time clock module (i 2 c bus) i 2 c bus interface overview of i 2 c - bus the i 2 c bus supports bi - directional communications via two signal lines: the sda (data) line and sc l (clock) line. a combination of these two signals is used to transmit and receive communication start/stop signals, data signals, acknowledge signals, and so on. both the scl and sda signals are held at high level whenever communications are not being per formed. the starting and stopping of communications is controlled at the rising edge or falling edge of sda while scl is at high level. during data transfers, data changes that occur on the sda line are performed while the scl line is at low level, and on the receiving side the data is captured while the scl line is at high level. in either case, the data is transferred via the scl line at a rate of o ne bit per clock pulse. the i 2 c bus device does not include a chip select pin such as is found in ordinary l ogic devices. instead of using a chip select pin, slave addresses are allocated to each device and the receiving device responds to communications only when i ts slave address matches the slave address in the received data. system configuration all ports connected to the i 2 c bus must be either open drain or open collector ports in order to enable and connections to multiple devices. scl and sda are both connected to the vdd line via a pull - up resistance. consequently, scl and sda are both held at high leve l when the bus is released (when communication is not being performed). fig 1. system configuration master mcu slave rtc other peripheral device v cc sda scl note: when there is only one master, the mcu is ready for driving scl to "h" and r p of scl may not required. r p r p
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 13 pt7c43 38 33 real - time clock module (i 2 c bus) starting and stopping i 2 c bus communications fig 2. starting and stopping on i 2 c bus 1) start condition, repeated start condition, and stop condition a ) start condition sda level changes from high to low while scl is at high level b ) stop condition sda level changes from low to high while scl is at high level c ) repeated start condition (restart condition) in some cases, the start condition occurs between a previous start condition and the next stop condition, in which case the second start condition is distinguished as a restart condition. since the required status is the same as for the start condition, the sda level changes from high to low while scl is at high level. 2) data transfers and acknowledge responses during i 2 c - bus communication a) data transfers data transfers are performed in 8 - bit (1 byte) units once the start condition has occurred. there is no limit on the amount (bytes) of data that are transferred between the start condition and stop condition. the address auto increment function operates during both write and read operations. updating of data on the transmitter (transmitting side)'s sda line is performed whil e the scl line is at low level. the receiver (receiving side) captures data while the scl line is at high level. *note with caution that if the sda data is changed while the scl line is at high level, it will be treated as a start, restart, or stop condition.
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 14 pt7c43 38 33 real - time clock module (i 2 c bus) b) data acknowledge response (ack signal) when transferring data, the receiver generates a confirmation response (ack signal, low active) each time an 8 - bit data segment is received. if there is no ack signal from the receiver, it indicates that normal communication has not been established. (this does not include instances where the master device intentionally does not generate an ack signal.) immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on th e scl line, the transmitter releases the sda line and the receiver sets the sda line to low (= acknowledge) level. after transmitting the ack signal, if the master remains the receiver for transfer of the next byte, the sda is released at t he falling edge of the clock corresponding to the 9th bit of data on the scl line. data transfer resumes when the master becomes the transmitter. when the master is the receiver, if the master does not send an ack signal in response to the last byte sent fr om the slave, that indicates to the transmitter that data transfer has ended. at that point, the transmitter continues to release the sda and aw aits a stop condition from the master. slave address the i 2 c bus device does not include a chip select pin suc h as is found in ordinary logic devices. instead of using a chip select pin, slave addresses are allocated to each device. all communications begin with transmitting the [start condition] + [slave address (+ r/w specification)]. the receiving devic e respo nds to this communication only when the specified slave address it has received matches its own slave address. slave addresses have a fixed length of 7 bits. see table for the details. an r/w bit is added to each 7 - bit slave address during 8 - bit transfers . table operation transfer data slave address r / w bit bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 read d1 h 1 1 0 1 0 0 0 1 (= read) write d0 h 0 (= write) i 2 c buss basic transfer format scl from master 1 2 8 9 sda from transmitter (sending side) sda from receiver (receiving side) release sda low active ack signal s start indication p stop indication sr restart indication a rtc acknowledge a master acknowledge
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 15 pt7c43 38 33 real - time clock module (i 2 c bus) 1) write via i 2 c bus 2) read via i 2 c bus a) standard read b) simplified read note: 1. the above steps are an example of transfers of one or two bytes only. there is no limit to the number of bytes transferred during actual communications. 2. 49h, 4ah are used as test mode address. customer should not use the addresses. slave address (7 bits) 1 1 0 1 0 0 0 0 write addr. setting slave address + write specification address specifies the write start address. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit a p write data s a a c k a c k a c k start stop slave address (7 bits) 1 1 0 1 0 0 0 0 write slave address + write specification address specifies the read start address. addr. setting a s slave address (7 bits) 1 1 0 1 0 0 0 1 read slave address + read specification data read (1) data is read from the specified start address and address auto increment. a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p sr 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit data read (2) address auto increment to set the address for the next data to be read. a c k n o a c k a a c k a c k a c k a start stop restart data read (2) address register auto increment to set the address for the next data to be read. data read (1) data is read from the address pointed by the internal address register and address auto increment. slave address (7 bits) 1 1 0 1 0 0 0 1 read a bit 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit /a p s 7 6 5 4 3 2 1 0 bit bit bit bit bit bit bit bit a c k n o a c k a c k a stop start slave address + read specification
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 16 pt7c43 38 33 real - time clock module (i 2 c bus) mechanical information we (lead free and green soic - 8) min max a 1.350 1.750 a1 0.100 0.250 a2 1.350 1.550 b 0.330 0.510 c 0.170 0.250 d 4.700 5.100 e 3.800 4.000 e1 5.800 6.200 e l 0.400 1.270 0 8 symbol dimensions in millimeters 1.27 bsc note: 1) controlling dimensions in millimeters. 2) ref : jedec ms - 012e/aa
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| |||||| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||| 12 - 07 - 0001 pt 0321 - 6 07/04 /12 17 pt7c43 38 33 real - time clock module (i 2 c bus) ue(lead free and green msop - 8) ordering information part number package code package pt7c433833we w lead free and gre en 8 - pin soic PT7C433833UE u lead free and green 8 - pin msop note: ? e = pb - free and green ? adding x suffix = tape /r eel pericom semiconductor corporation ? 1 - 800 - 435 - 2336 ? www.pericom.com pericom reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. pericom does not assume any responsibility for use of any circuitry described other than the circuitry embodied in pericom product. the company makes no representations that circuitry described herein is free from patent infringement or other rights, of pericom . min max a 0.82 1.10 a1 0.02 0.15 a2 0.75 0.95 b 0.25 0.38 c 0.09 0.23 d 2.90 3.10 e 2.90 3.10 e1 4.75 5.05 e l 0.40 0.80 0 6 symbol dimensions in millimeters 0.65 bsc note: 1 ) controlling dimensions in millimeters. 2 ) ref : jedec mo - 187 e/ba

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